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1 acd confidential. do not reproduce. use under non-disclosure agreement only. data sheet: ACD81024 24 ports single chip 10base-t ethernet switch designed for desktop environment last update: 11/30/97 acd confidential material for acd authorized customer use only. no reproduce or redistribution without acds prior permission. preliminary please check acds website for update information before starting a design web site: http://www.acdcorp.com/tech.html or contact acd at: email: support@acdcorp.com tel: 510-797-4888x115 fax: 510-494-5730
2 acd confidential. do not reproduce. use under non-disclosure agreement only. table of contents 1. general description 2. main features 3. operational description 4. functional description 5. special handling on ieee 802.3 6. pin diagram and pin table 7. signal description 8. signal wave forms 9. electrical specifications 10. packaging
3 acd confidential. do not reproduce. use under non-disclosure agreement only. switch fabric switch control led control lookup engine mac mac phy txrx port 2 mac port 1 port 24 port 3 mac phy phy phy phy txrx phy system block diagram 1. general description ACD81024 is a single chip system integration of an entire 24 port ethernet switch, specifically designed for networks compliance with ieee 802.3 10base-t stan- dard. all active components of a 24 port ethernet switch system, including the 10base-t transceivers, clock and data recovery circuitry, manchester endec, media access control logic, lookup engine, switch fabric, and switch control logic are all integrated into a single semiconductor chip. ACD81024 can be used to build a desktop class 10base-t ethernet switch system with very low cost and very short time-to-market cycle. to build a marketable ethernet switch system using ACD81024 requires no more than a dc power supply, emi/rfi filter/transformer modules, rj45 connectors, leds, and led drivers. 2. main features single chip integration of a ethernet switch system supports 24 10base-t ports very short time-to-market cycle no need of external memory no need of external glue logic built-in 10base-t transceiver built-in clock and data recovery circuitry smart squelch intelligence polarity detection and correction link integrity pulse detection and generation manchester endec media access control logic fcs verification storage of one mac address per port lookup engine non-blocking switching fabric fabric control logic back-pressure congestion control automatic mac address learning cut-through switching mode with constant low latency < 16 us led display of each ports link status, transmit, receive, collision, congestion, jabber, and fcs error indication one expansion port for connecting with other interconnection devices line speed forwarding rate 208 pin pqfp package with built-in heat-sink single 5v power supply
4 acd confidential. do not reproduce. use under non-disclosure agreement only. 3. operational description ACD81024 ethernet switch is composed by six types of logic modules: the physical layer (phy) circuitry, the media access control (mac) logic, the lookup engine, the switching fabric, the fabric control logic, and the led control logic. on the receiving side, the phy circuitry converts the analog voltages coming from the unshielded twist pair cable into digital signals suitable for digital processing, and decodes the received data in manchester code into nrz code. on the transmitting side, the phy circuitry translates the data to be transmitted from nrz code into manches- ter code, and then converts the data into analog signals suitable to drive unshielded twist pair cable. the mac logic of a port controls the transmit, re- ceive, defer, and congestion control process of the port. the lookup engine provides mapping between a destination mac address and a destination port number. the switching fabric is used to establish communication channels between the source ports and the associated destination ports. the fabric control logic controls the construction/destruction of the communication channels. the led control logic displays various kinds of port status of the switch. ACD81024 is designed as a desktop class ethernet switch. only one dte with one mac address can be connected to each port of ACD81024, except the expansion port. when an ethernet frame comes from a data termina- tion device (dte) through a 10base-t network media (utp) into a source port of ACD81024 switch, the signal, encoded in manchester code, is amplified by the twist pair receiver circuitry of the source port and converted into a nrz data signal and a recovered clock signal by the decoder circuitry of the source port. the nrz data signal is then processed by the mac logic of the source port. the information of the destination address (da) and the source address (sa) embedded inside the frame are retrieved. the sa is used to update the ports mac address stored in the lookup engine. the da is used to identify the destination port. once the destination port is identi- fied, the fabric control logic checks the status of the destination port(s) to see if the destination port(s) is ready to receive the data. if so, the fabric control logic establishes the communication channel(s) between the source port and the destination port(s) inside the switching fabric. the mac logic of the source port forwards the received data to the estab- lished the communication channel in the switching fabric. the mac logic of the destination port(s) receives the data from the communication channel in the switching fabric and forwards the data to the destination ports physical layer circuitry. the manchester encoder circuitry translates the data into manchester code and sends to the ports twist pair transmitter circuitry. the transmitter circuitry converts the data into analog levels suitable to drive the 10base-t network media between the switch and the destination dte. if collision is detected during a transmission process, the destination port mac logic will end the frame with a jam pattern. the source port mac logic will stop forwarding the frame data and send a jam pattern back to the source dte. if the destination port headed by an incoming frame is not ready to receive the data, the mac logic of the source port will send a jam pattern to the source dte. according to ieee 802.3 csma/cd scheme, the source dte will retransmit the frame after a pre- determined back-off time period. in order to prevent the source dte from sending the frame before the destination port is ready, ACD81024 continuously sends a back pressure signal to the source dte to cause its carrier sense signal to be asserted. the transmit-defer-on-carrier-sense nature of csma/cd scheme will prevent the source dte from sending the frame as long as the carrier sense signal is asserted. the back pressure signal is released when the destination port(s) is ready to receive new frame. different from a typical ethernet frame switch, ACD81024 does not store the received data into data buffer. instead, it sends the data directly to the destination port in cut-through mode. in collision domain isolation perspective, ACD81024 behaves like a shared-media repeater. once collision is detected on the destination port, a jam pattern is sent to the source dte to force collision detection. differ- ent from a shared-media repeater, collision is caused by concurrent transmission activities of the source dte and the destination dte(s), not any dte connected with the switch. in other words, the colli- sion domain is minimized to the source port and the corresponding destination port(s). 4. functional description 4.1 phy module ACD81024 provides built-in twist pair transmitter/ receiver (transceiver) circuitry for each port. besides, each phy module also contains the logic for polarity detection and automatic correction, manchester code encoding and decoding, clock data recovery, and link pulse detection and generation. all circuits are implemented to be 100% compatible with ieee 802.3 requirement.
5 acd confidential. do not reproduce. use under non-disclosure agreement only. t wist pair t ransmitter the twist pair transmitter converts the digital output signal into analog voltages necessary to drive unshielded twist pair cable. different from most other implementations, the transmitter circuitry inside ACD81024 uses two output pins (as opposed to four) and internally generates emphasis/de-emphasis voltage levels required to compensate for the twist pair cable. the waveform of each kind of output signal is described in the chapter of signal wave- forms. t wist pair receiver the twist pair receiver converts the analog voltages coming from the unshielded twist pair cable into ttl level signals suitable for digital processing. each twist pair receiver of ACD81024 is equipped with a smart squelch circuitry to ensure that noise on the receive pair will not be treated as valid frame data signals. the squelch circuitry employs a combination of both amplitude and timing measurement to deter- mine the validity of received data signal. only valid data will be passed to the manchester decoder circuitry. validity of data is determined by following three conditions: 1 the signal crosses the positive threshold level of +365 mv or negative threshold level of -365 mv. 2 the signal has to cross the other threshold level within 150 ns. 3 the signal has to cross the original threshold within 150 ns. the waveform of signal received by the smart squelch circuitry is described in the chapter of signal waveforms. polarity detection and correction polarity detection circuitry uses the incoming link pulses to check for polarity reversal. if the polarity of the signal is detected to be reversed, the polarity correction logic automatically inverts the receiving pair. therefore, the mac logic circuitry will always receive the signal in correct polarity. manchester decoding on the receive side, after passing through the polarity detection and automatic correction circuitry, the incoming signal is processed by the manchester decoder circuitry. the manchester decoder converts the manchester code data signal into nrz data signal and at same time, generates a recovered clock signal. the recovered clock signal is used to latch the nrz data into a synchronization fifo. the nrz data is read out of the fifo using the system clock. manchester encoding on the transmit side, the nrz data coming from the mac logic is converted into manchester code by the manchester encoder circuitry. the data is then passed to the 10base-t transceiver circuitry for transmission onto the network media. link pulse detection on the receive side, each phy module has a link pulse detection circuitry. if no link pulse is received for 50 ms, a link test fail signal will be sent to the ports mac logic circuitry to cause it enter the link fail state. in link fail state, the link led signal of the port is deserted. however, transmission from the port is not disabled. any traffic heading for this port will still be forwarded to it. when the phy circuitry receives a valid link pulse, or receives a continuous bit stream, it signals the mac logic for valid link status and causes mac logic enter the link pass state immediately. the waveform of a link pulse to be detected by the link pulse detector is shown in the chapter of signal waveforms. the link pulse detection function can be disabled by pulling low the lnke signal. link integrity pulse generation on the transmit side, each phy module has a link pulse generation circuitry. when there is no transmis- sion activity on the transmission pair, the link pulse generation circuitry generates one link pulse for every 16 ms. the width of the link pulse is 100ns. the waveform of the link pulse generated by ACD81024 is shown in the chapter of signal waveforms. 4.2 mac module the mac module controls the transmit, receive, defer, and congestion control process of a port, according to ieee 802.3 standard. frame format ACD81024 assumes the data frame coming into the switch have the following format: where, preamble sfd da sa type/len data fcs
6 acd confidential. do not reproduce. use under non-disclosure agreement only. preamble is repetitive pattern of 1010. of any length longer than 30 bits. sfd (start frame delimiter) is defined as an octet pattern of 10101011. da is a 48-bit field which specifies the mac address of the dte to which the frame is head- ing. if the first bit of da is 1, ACD81024 will treat the frame as a broadcast/multicast frame and will forward the frame to all ports except the source port itself. sa is a 48-bit field which contains the mac address of the dte which is transmitting the frame to ACD81024. type/len field is a 2-byte field which specifies the type (dix ethernet frame) or length (ieee 802.3 frame) of the frame. ACD81024 will not try to interpret this field. data could be any information which is totally transparent to ACD81024. fcs (frame check sequence) is a 32-bit field of crc (cyclic redundancy check) value based on the destination address, the source address, the type/length and the data field. ACD81024 will verify the fcs field for each frame. the proce- dure of computing fcs is described in section of fcs calculation. destination address processing as a frame comes into a port of ACD81024, the destination address field embedded inside the frame is retrieved and passed to the lookup engine to match it with the mac addresses stored in source mac address registers of all ports. the destination port is found if a match is found. source address learning as a frame comes into a port of ACD81024, the value of the source address embedded inside the frame is automatically read into a data register. at the end of the frame, if there is no fcs error and, if there is no value stored in the mac address register of the source port, or if the value of this new source address is different than the ports current mac address, the recorded value is used to update the mac address register of the source port inside the lookup engine module. the value will be used by the lookup engine to match with the destination address embedded in a frame to identify the destination port. a ports mac address register is cleared on power- up, by hardware reset, or when the mac logic cir- cuitry enters its link fail state due to loss of link pulse reported by the phy module. unicast frame forwarding if the first bit of the destination address is 0, the frame is a unicast frame. the destination address is passed to the lookup engine which returns a destination port(s) number(s) to identify which port(s) should the frame be forwarded. if the lookup engine cannot find any match for the destination address, the frame will be forwarded to all the ports which has not learned its source address, plus the expansion port. the re- turned destination port number is passed to the fabric control logic which checks if the destination port(s) is ready to receive the frame. if it is, the switch control logic constructs the communication channel(s) between the source port and the destina- tion port(s). the source port mac logic forwards the incoming frame to the destination port(s) mac logic through the communication channel(s). while the data is forwarded, the mac logic of the destination port keeps on monitoring if collision occurs on the destination port. if so, the source port mac logic will send a jam pattern to the source dte. if the any one of the destination port(s) is not ready to receive the frame, the source port mac logic will start a conges- tion control process. the details of congestion control is explained in the section of congestion control. broadcast/multicast t raf fic handling if the first bit of the destination address is a 1, the frame is a multicast or broadcast frame. ACD81024 treats multicast frame the same as broadcast frame. for a broadcast frame, the destination port contains all the ports of the switch except the source port itself. the fabric control logic checks if all the destination ports are ready for receiving this broadcast frame. if all of the destination ports are ready to receive the frame, the source port will forward the frame data to all destination ports in cut-through mode. if any one of the destination ports is not ready, the source port mac logic will send a jam pattern to the source dte, followed by back pressure signal. when all ports are ready to transmit the broadcast frame, the back pressure signal applied to the source dte will be removed. upon the time the source dte retransmits the broadcast frame to the switch, the frame data is forwarded to all destination ports. fcs calculation each port of ACD81024 has a crc checking logic to
7 acd confidential. do not reproduce. use under non-disclosure agreement only. verify if the received frame has a valid fcs value. wrong fcs value is an indication of a fragmented frame or a frame with frame bit error. the method of calculating the crc value of the frame data is by using following polynomial g(x) = x 32 + x 26 + x 23 + x 22 + x 16 + x 12 + x 11 + x 10 + x 8 + x 7 + x 5 + x 4 + x 2 + x + 1 as a divider to divide the bit sequence of the incoming frame, beginning with the first bit of destination address field, up to the end of the data field. the result of the calculation, which is the residue after the polynomial division, is the value of frame check sequence. the value should be equal to the fcs field appended at the end of the frame. if the value does not match with the fcs field of the frame, the frame bit error led of the port will be turned on once. short frame handling if a frame is shorter than 140 bits after the sfd fields, it will not be forwarded to the destination port(s). frames longer than 140 bits will be forwarded to the destination port(s) no matter if it passes the fcs checking or not. jabber lockup protection if an incoming frame is detected to be longer than 50,000 bits, it will be broken by the jabber protection circuitry inside the mac logic. the frame bits later than 50,000 bit will be forwarded to nowhere. a jabber error is reported through the jabber error led of the port. after proper inter-frame-spacing time, the mac logic of the port will be ready to receive next frame. t ransmit t ime w atchdog control the watchdog circuitry inside each mac logic keeps on monitoring the number of bits transmitted by the destination mac logic. if the length of the transmitted frame is longer than 38,000 bit, the watchdog circuitry will break the frame and append a jam pattern to the end. this function can be disabled by pulling the wche signal low. preamble bit handling the preamble bit in the header of each frame will be used to synchronize the mac logic circuitry with the incoming bit stream. the minimum length of the preamble is 30 bits and there is no limit on the maximum length of preamble. the preamble will be regenerated by mac logic of ACD81024 with exact length of 56 bits as the frame is transmitted out of the destination port(s). inter frame spacing handling if the silent time between frames coming from a dte is less than the minimum ifs requirement of 96bt, ACD81024 will send a jam pattern to the correspond- ing source dte just like a congestion has occurred. collision detection and handling while the mac logic of a destination port is transmit- ting data to the destination dte, if there is any data coming from the destination dte (or say if the carrier sense signal is raised up by the phy module of the destination port), collision is detected. collision will cause the mac logic of both the destination port and the source port to enter a collision handling state. on the destination port side, current transmit process is aborted and a jam pattern is appended to the end of the broken frame. on the source port side, a jam pattern is sent to the source dte, beginning with 56 bit preamble and a valid start of frame delimiter. the jam pattern will cause the source dte to stop transmitting and retransmit the frame after proper back-off time. congestion detection and handling if a destination port headed by an incoming frame is in the process of receiving or transmitting or deferring on inter-frame-spacing time, the fabric control logic signals the source port mac logic that the destination port is not ready. the source port mac logic then enters a congestion control state. in congestion control state, the mac logic of the source port first sends a jam pattern to the source dte to force a collision, and then, after proper inter-frame-spacing time, sends a continuous back pressure signal to the source dte. if collision is detected on the back pressure signal, the mac logic will end the back pressure pattern with a jam pattern, wait for mini- mum ifs time, and send the back pressure signal again. when the destination port(s) is available, the back pressure signal is ended with a jam pattern. expansion port handling port 24 of ACD81024 is designed to be the expansion port (or say the dumping port). it can be used for uplink connection or for ordinary desktop connection. that is, port 24 can be connected with a repeater hub, a work-group switch, a router, or any type of interconnection device compliance with ieee 802.3 10base-t standard. ACD81024 will direct following frames to the expansion port:
8 acd confidential. do not reproduce. use under non-disclosure agreement only. 1 frame with unicast destination address and does not match with any port mac address of the switch 2 frame with broadcast/multicast address 3 frame dumped to keep dte address alive (see section of address keep alive handling) address keep alive handling the address learned by an interconnection device has a limited life cycle. to keep the address of the dtes connected with the switch alive in the intercon- nection device connected with the expansion port of the switch, ACD81024 can be set to dump at least one frame to the expansion port for every five min- utes. this function can be disabled by pulling low of the dmpe signal. half duplex operation mode ACD81024 can only work in half duplex mode. any concurrent transmit and receive activities will be treated as collision. spanning t ree handling only port 24 of ACD81024 can be used to connect with an interconnection device which support multiple mac addresses. all other ports of ACD81024 should only be used to connect with one desktop dte with only one mac address. therefore, it is not necessary to handle spanning tree protocol to avoid formation of a loop. latency the latency, defined by the time difference between the first bit enters into ACD81024 and first bit comes out of ACD81024, is a constant value of 146 bit time. collision domain different from typical ethernet switch, ACD81024 does not isolate the collision domain between the source dte and the destination dte. therefore, the latency of ACD81024 needs to be counted as part of the delay path. the delay on the forward path is 146 bit times. the delay on the backward path (for collision detection) is 4 bit times. 4.3 lookup engine module the lookup engine is responsible to provide mapping between a mac address and a port number. it contains one mac address storage for each port. the value of sa embedded inside the frame is used to update the value of the mac address storage of the source port. the value of da is used to identify the destination port. 4.4 switch fabric module switch fabric is responsible for establishing the connection channel(s) from a source port to the corresponding destination port(s). ACD81024 imple- ments a cross-bar type switch fabric that allows high efficient multiple channels of simultaneous connec- tions. 4.5 fabric control module fabric control logic controls the process of construc- tion/destruction of the communication channel in the switch fabric. before a connection can be made, fabric control logic first checks the status of the destination port(s), to see if it is suitable to open the path. fabric control logic is responsible to notify the source mac logic if the requested connection has been made or not. 4.6 led control module just like a shared media repeater system, ACD81024 is designed to have a wide variety of led indicators for simple system administration. the display update is completely autonomous and merely requires low speed ttl or cmos devices as led drivers. the status display is designed to be flexible to allow the system designer to choose those indicators appropri- ate for the specification of the equipment. there are two led control signals. ledvld signal is used to indicate the start and end of the led data signal. ledclk signal is a 1mhz clock signal. the rising edge of ledclk can be used to latch the led data signal into the led driver circuitry. the led data signals contain lnk, xmt, rcv, col, fbe, jbr, addr and bsy, which represent link status, transmit status, receive status, collision indication, frame bit error, jabber error, port address learned status, and congestion control status respectively. these status signals are sent out sequentially from port one to port twenty-four, once every 100ms. for details about the timing diagrams of the led signals, refer to the chapter of signal waveforms. 5. special handling on 802.3
9 acd confidential. do not reproduce. use under non-disclosure agreement only. general speaking, ACD81024 is designed to comply with ieee 802.3 standard. ACD81024 has also been proved to work perfectly with ieee 802.3 compatible devices. however, there are a few creative features implemented on ACD81024 which deviate a little from ieee 802.3 standard. the following is a description on these features: collision backof f t ime period since ACD81024 does not store the received traffic, each output port of ACD81024 does not schedule the retransmission as a bridge type device does. when collision is detected on an output port, both the source dte and the destination dte will receive a jam pattern to force collision detection on both sides. ACD81024 behaves like a middle man. it is the source and destination dtes which will follow the truncated binary exponential backoff process defined by the csma/cd scheme to control the retransmis- sion time. moreover, if there are multiple source dtes trying to send data to the same destination dte at same time, ACD81024 will remove the back pressure signal applied to one of these source ports to allow the attached source dte to start sending data to the destination dte. ACD81024 also monitors the number of consecutive collisions occurred on each port. when the number of collisions on a port is higher than the threshold value of three, the port has higher priority than other input ports to get the com- munication channel. therefore, ACD81024 eliminates the draw backs of the channel capturing feature on networks using repeater hubs. collision-jam propagation delay ACD81024 does not isolate the collision domain between its input port and output port. instead, it uses jam plus back pressure signal for congestion control. ieee 802.3 specifies that the collision-jam propaga- tion delay on a repeater set with internal 10-base-t maus on input and output ports should be less than 20.5 bit times. since ACD81024 is a switching device, collision cannot be detected until the destination port is identified. as a result, the collision-jam propagation delay on ACD81024 is 150 bit times. therefore, care should be taken when using ACD81024 in a multisegment networking environment. the summa- tion of the round trip delay should not exceed 512 bit times, and ACD81024 contributes 150 bit times for round trip propagation delay.
10 acd confidential. do not reproduce. use under non-disclosure agreement only. 6. pin diagram and pin description ACD81024 1 5 10 15 20 25 30 35 40 45 50 155 150 145 140 135 130 125 120 115 110 105 55 60 65 70 75 80 85 90 95 100 205 200 195 190 185 180 175 170 165 160 txp_1 txn_1 dvss rxp_1 rxn_1 avdd avss rxp_2 rxn_2 dvdd txp_2 txn_2 txp_3 txn_3 dvss dvdd rxp_3 rxn_3 avdd avss rxp_4 rxn_4 dvdd txp_4 txn_4 dvss txp_5 txn_5 dvss rxp_5 rxn_5 avdd rxp_6 rxn_6 avss txp_6 txn_6 dvss dvdd txp_7 txn_7 dvss dvdd rxp_7 rxn_7 avdd vss3 rxp_8 rxn_8 dvss txp_8 txn_8 dvdd txp_9 txn_9 dvss dvdd rxp_9 rxn_9 dvss dvdd rxp_10 rxn_10 avdd avss txp_10 txn_10 avss txp_11 txn_11 dvdd rxp_11 rxn_11 avdd avss rxp_12 rxn_12 dvss txp_12 txn_12 dvdd txp_13 txn_13 dvss dvdd rxp_13 rxn_13 avdd avss rxp_14 rxn_14 dvss dvdd txp_14 txn_14 dvss dvdd txp_15 txn_15 dvss dvdd rxp_15 rxn_15 avss dvdd txn_23 txp_23 dvss txn_22 txp_22 dvdd rxn_22 rxp_22 avdd avss rxn_21 rxp_21 dvdd dvss txn_21 txp_21 dvdd txn_20 txp_20 dvss dvdd rxn_20 rxp_20 avdd avss rxn_19 rxp_19 dvss txn_19 txp_19 dvdd txn_18 txp_18 dvss rxn_18 rxp_18 avss avdd rxp_17 rxn_17 dvss dvdd txn_17 txp_17 dvdd txn_16 txp_16 dvss rxn_16 rxp_16 avdd dvss rxp_23 rxn_23 avss avdd ledvld ledclk dvss dvdd fbe addr jbr fbsy col rcv xmt lnk dvdd dvss wdge resetn dmpe sqle pole lnke dvdd clk80 dvss dvss nc nc dvss nc nc nc dvdd nc dvdd nc nc nc nc nc dvss dvdd rxp_0 rxn_0 avss avdd txp_0 txn_0 dvdd
11 acd confidential. do not reproduce. use under non-disclosure agreement only. table 6.1 - pin list pin name pin name pin name pin name pin name pin name pin name pin name 1 txp_1 27 txp_5 53 dvdd 79 txp_12 105 avdd 131 avss 157 dvss 183 clk80 2 txn_1 28 txn_5 54 txp_9 80 txn_12 106 rxp_16 132 avdd 158 rxp_23 184 dvss 3 dvss 29 dvss 55 txn_9 81 dvdd 107 rxn_16 133 rxp_20 159 rxn_23 185 dvss 4 rxp_1 30 rxp_5 56 dvss 82 txp_13 108 dvss 134 rxn_20 160 avss 186 nc 5 rxn_1 31 rxn_5 57 dvdd 83 txn_13 109 txp_16 135 dvdd 161 avdd 187 nc 6 avdd 32 avdd 58 rxp_9 84 dvss 110 txn_16 136 dvss 162 ledvld 188 dvss 7 avss 33 rxp_6 59 rxn_9 85 dvdd 111 dvdd 137 txp_20 163 ledclk 189 nc 8 rxp_2 34 rxn_6 60 dvss 86 rxp_13 112 txp_17 138 txn_20 164 dvss 190 nc 9 rxn_2 35 avss 61 dvdd 87 rxn_13 113 txn_17 139 dvdd 165 dvdd 191 nc 10 dvdd 36 txp_6 62 rxp_10 88 avdd 114 dvdd 140 txp_21 166 fbe 192 dvdd 11 txp_2 37 txn_6 63 rxn_10 89 avss 115 dvss 141 txn_21 167 addr 193 nc 12 txn_2 38 dvss 64 avdd 90 rxp_14 116 rxn_17 142 dvss 168 jbr 194 dvdd 13 txp_3 39 dvdd 65 avss 91 rxn_14 117 rxp_17 143 dvdd 169 fbsy 195 nc 14 txn_3 40 txp_7 66 txp_10 92 dvss 118 avdd 144 rxp_21 170 col 196 nc 15 dvss 41 txn_7 67 txn_10 93 dvdd 119 avss 145 rxn_21 171 rcv 197 nc 16 dvdd 42 dvss 68 dvss 94 txp_14 120 rxp_18 146 avss 172 xm t 198 nc 17 rxp_3 43 dvdd 69 txp_11 95 txn_14 121 rxn_18 147 avdd 173 lnk 199 nc 18 rxn_3 44 rxp_7 70 txn_11 96 dvss 122 dvss 148 rxp_22 174 dvdd 200 dvss 19 avdd 45 rxn_7 71 dvdd 97 dvdd 123 txp_18 149 rxn_22 175 dvss 201 dvdd 20 avss 46 avdd 72 rxp_11 98 txp_15 124 txn_18 150 dvdd 176 wdge 202 rxp_0 21 rxp_4 47 avss 73 rxn_11 99 txn_15 125 dvdd 151 txp_22 177 resetn 203 rxn_0 22 rxn_4 48 rxp_8 74 avdd 100 dvss 126 txp_19 152 txn_22 178 dmpe 204 avss 23 dvdd 49 rxn_8 75 avss 101 dvdd 127 txn_19 153 dvss 179 sqle 205 avdd 24 txp_4 50 dvss 76 rxp_12 102 rxp_15 128 dvss 154 txp_23 180 pole 206 txp_0 25 txn_4 51 txp_8 77 rxn_12 103 rxn_15 129 rxp_19 155 txn_23 181 lnke 207 txn_0 26 dvss 52 txn_8 78 dvss 104 avss 130 rxn_19 156 dvdd 182 dvdd 208 dvdd
12 acd confidential. do not reproduce. use under non-disclosure agreement only. table 7.1 - 10base-t interface group: mnemonic type i/o active description txp_0 ~ txp_23 diff o ethernet 10base-t twisted pair transmit output positive txn_0 ~ txn_23 diff o ethernet 10base-t twisted pair transmit output negative rxp_0 ~ rxp_23 diff i ethernet 10base-t twisted pair receive input positive rxn_0 ~ rxn_23 diff i ethernet 10base-t twisted pair receive input negative table 7.2 - configuration interface group mnemonic type i/o active description lnke cmos i high link integrity detection function enable pole cmos i high automatic polarity detection and correction function enable sqle cmos i high smart squelch intelligence function enable dmpe cmos i high periodic dumping function enable wdge cmos i high transmit time watchdog function enable table 7.3 - led interface group mnemonic type i/o active description lnk cmos o high link status indication signal xmt cmos o high transmit indication signal rcv cmos o high receive indication signal col cmos o high collision indication signal bsy cmos o high congestion control indication signal jbr cmos o high jabber error indication signal addr cmos o high port address learned status indication signal fbe cmos o high frame bit error (fcs error or alignment error) indication signal ledvld cmos o high led valid signal ledclk cmos o led clock signal table 7.4 - misc. signal group mnemonic type i/o active description dvdd i +5v power input for digital circuitry avdd i +5v power input for analog circuitry dvss i ground power input for digital circuitry avss i ground power input for analog circuitry clk80 cmos i system clock signal from a 80.000mhz clock oscillator resetn cmos i low system reset negative, low active 7. signal description the interface signals of ACD81024 can be divided into four groups. the description of all kinds of signals in each group are shown below:
13 acd confidential. do not reproduce. use under non-disclosure agreement only. figure 8.1: data receiving with smart squelch intelligent end of package start of package < 150 ns < 150 ns > 150 ns +365mv -365mv 8. signal waveforms 8.1 twisted pair receiver figure 8.2: link pulse detection 365 mv < 200 ns > 25 ns
14 acd confidential. do not reproduce. use under non-disclosure agreement only. figure 8.3: preamble signal generation 8.2 twisted pair transmitter 100ns 100ns +2.5 v -2.5 v figure 8.4: end of frame pattern generation 300 ns -2.5 v +2.5 v
15 acd confidential. do not reproduce. use under non-disclosure agreement only. figure 8.5: link pulse generation +2.5 v 200 ns figure 8.6: led data signal lnk xmt rcv col bsy jbr addr fbe ledvld ledclk p 1 p 2 p 3 p 4 p 5 p 6 p 7 p 8 p 9 p 10 p 11 p 12 p 13 p 14 p 15 p 16 p 17 p 18 p 19 p 20 p 21 p 22 p 23 p 24 8.3 led data signal
16 acd confidential. do not reproduce. use under non-disclosure agreement only. dc supply volta g e vdd 0.3v ~ +7.0v dc input current iin +/ 10 ma dc input volta g e vin 0.3 ~ vdd + 0.3v dc output volta g e vout 0.3 ~ vdd + 0.3v stora g e temperature tstg 40 to +125oc supply volta g e vdd 5v, +/-5% operatin g temperature ta 0oc ~ 85 oc power dissipation pd 4w (typ.) 9. electrical specification absolute maximum ratings operation at absolute maximum ratings is not implied. exposure to stresses outside those listed could cause permanent damage to the device. recommended operation conditions
17 acd confidential. do not reproduce. use under non-disclosure agreement only. pqfp-208 30.6 0.2 28.0 0.2 0.1 3.32 30.6 0.2 28.0 0.2 1.25 0.1 0.5 +/- +/- +/- +/- 10. packaging

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